9827

Applied Voltage on an Ideal MOS Capacitor

This Demonstration simulates the effect of an external bias on an MOS capacitor. The four plots show the electric field (), the corresponding potential of the capacitor (), the carrier density of the semiconductor from the junction through the depletion layer (), and the band profiles of the semiconductor and the metal, all as functions of the position () inside the capacitor. You can vary the gate voltage bias to explore all three regimes of biasing: hole accumulation, depletion, and inversion.

SNAPSHOTS

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DETAILS

This Demonstration simulates an ideal NMOS capacitor constructed using silicon, silicon oxide, and an aluminum electrode. The variable is the thickness of the oxide layer; , , , and are, respectively, the electric fields and the electrostatic potentials applied to the oxide and to the semiconductor; and are the hole and electron densities inside the semiconductor far away from the interface; and is the concentration of positive dopant ions inside the semiconductor. is the Fermi level inside the metal and the semiconductor, while is the position of the Fermi level of the intrinsic semiconductor; hence it lies in the middle of the band gap. and are the conduction and valence bands of the semiconductor.
Snapshot 1: capacitor in the hole accumulation regime; hole density increases near the semiconductor-oxide interface
Snapshot 2: capacitor with the flat band voltage applied; the bands are flat in the semiconductor and there is no longer any electric field or potential
Snapshot 3: capacitor in the inversion regime; electron density at the interface approaches the hole density of the bulk semiconductor
Several assumptions are made to simplify the model. The electric field is assumed constant inside the oxide and linear in the depletion layer. The carrier density in the metal is assumed to be infinite, so the band profile stays flat inside it. A Boltzmann approximation is assumed for carrier densities in the semiconductor. The voltage bias cannot exceed the threshold voltage, since a simple model for the inversion layer is missing. Also, interface trap states are neglected.
Reference
[1] J. Singh, Semiconductor Devices: Basic Principles, New York: Wiley, 2000.
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